This invention is directed to a current-supplying integrated circuit having multi-output which can be used in a printing device such as an LED printer or a thermal printer and, in particular, to a current-supplying integrated circuit which has a plurality of outputs for generating currents of varied strength to adjust the light strength for or the print density by each bit of the printing elements.
A conventional LED printer has an array of LEDs corresponding to a line to be printed, and the duration of each LED's emission is controlled so that desired print density can be obtained. A typical LED driving circuit provided in an LED printer is illustrated in FIG. 17. The driving circuit comprises a main frame 1, which includes, for example, a computer for generating data signals and the like, an integrated circuit 3 for driving an LED print head, and a ROM 4 for storing correction codes. The LED driving circuit also has a microprocessor 5 which, based on the data signals generated by main frame 1, controls integrated circuit 3 and ROM 4. Integrated circuit 3, which drives the LED print head, includes an output-transistor array 6 consisting of a plurality of field-effect transistors, each of which is connected to one LED of an LED-array integrated circuit 7. Integrated circuit 3 functions to control the period of emission of the individual LEDs so that variation in the quantity of emission among the LEDs can be corrected.
Microprocessor 5 in the LED driving circuit generates and delivers a control signal to ROM 4 on receiving the data signal for a line of print from main frame 1, so as to obtain correction code date from ROM 4. Microprocessor 5 then corrects the individual bits of the line of printing data in accordance with the correction code data to thereby produce a line of corrected printing data. The corrected data is supplied to the flip-flop constituting the least significant bit of a shift register 8. The data correcting operation is carried out such that the bits of the line of printing data are sequentially converted into corrected data consisting of three latch cycles, each latch cycle being adjusted in the duty ratio of the driving signal for the LED.
If, for example, the LED at the left side in LED array integrated circuit 7 has the lowest emission strength among the LEDs in FIG. 17, the emission strength correcting operation is carried out as follows. A correction code representing a value of 7 is stored beforehand in the ROM at an address corresponding to the left-side LED. Main frame 1 provides microprocessor 5 with a line of printing data including one bit for driving the left-side LED. Upon receiving this bit, microprocessor 5 generates and supplies a control signal to ROM 4 to obtain therefrom the line of printing data, including the correction code valued 7, for the left-side LED. In response to the line of printing data, microprocessor 5 produces a series of three-bit signals as corrected data signals and delivers them to shift register 8 in response to a latch signal.
Referring now to FIG. 18, the printing operation of the lth line is as follows. The data signal for the lth line is first converted into three blocks of corrected data signals l.sub.1, l.sub.2 and l.sub.3. The first block of corrected data l.sub.1 is stored in shift register 8 in response to a clock signal and is supplied from shift register 8 to the latch array 9 in response to the latch signal L.sub.1. Since the first corrected data signal l.sub.1 has the logically high bit corresponding to the left-side LED, the left-side latch is maintained logically high. In synchronization with the delivery of the latch signal L.sub.1, microprocessor 5 delivers an enable signal having a pulse width of 4t to an output control circuit 10. Output control circuitry 10, which comprises an array of AND gates and voltage-level shift circuits (which are denoted simply as "AND" in FIG. 17), delivers a control ON signal to the left-side FET of transistor array 6 while the enable signal is being supplied from microprocessor 5. The left-side FET is shifted to on-state by the control ON signal and, during the on-state, permits current to pass from the power supply V.sub.ss to the left-side FET. Thus, the left-side LED is driven to emit light during the period of 4t. In turn, by the end of this 4t period, the second block of corrected data l.sub.2 has already been supplied to the shift register 8. Therefore, the second block of data is latched by the latch circuit in response to the next latch signal L.sub.2.
The second block of corrected data l.sub.2 includes a logically high bit corresponding to the left-side LED, and so the left-side latch circuit is shifted to be logically high and generates a logically high signal L.sub.2. The logically high signal L.sub.2, as well as an enable signal having a pulse width of 2t, are delivered to output control circuit 10, which drives the left-side LED through the left-side FET to thereby light the LED for the 2t period of time. Likewise, the third block of corrected data l.sub.3 has been stored in shift register 8 during the delivery of the enable signal of 2t width pulse. The third corrected data is latched by the latch circuit in response to the latch signal L.sub.3. At this time, the left-side latch circuit is also maintained logically high. The latch signal L.sub.3 and an enable signal having a pulse of 1t width are supplied to control circuit 10, so that the left-side FET is turned ON, which, in turn, makes the left-side LED emit for a 1t period.
As mentioned above, the enable signal includes the pulses 4t, 2t and 1t, each pulse being delivered to output control circuit 10 in response to one of the latch signals. In control circuit 10, the data signal is converted into three corrected data signals in a row in accordance with the blocks of corrected data l.sub.1, l.sub.2 and l.sub.3.
In the above, as the left-side LED has the weakest emission strength and the correction data stored for it in ROM 4 is the maximum value (=7), the LED is controlled to emit intermittently for the entire 7t period of time. Likewise, in response to the stored values in ROM 4, the LEDs are controlled in their emitting periods from 1t to 7t incrementally, so that the emission strength of the respective LEDs are adjusted and, therefore, the printing densities produced by the LEDs of different emission strength are adjusted to the desired level.
As mentioned above, the integrated circuit for driving the LED printer head controls the emitting period of each LED to adjust the total emission quantity of each LED to a desired quantity in order to avoid printing unevenness due to variation in emission strength among the LEDs or due to variation in current-carrying capacity among the FETs forming the output transistor array. In other words, the FET's ON-time periods are controlled by seven degrees through the respective three-latch cycles. However, this means that the adjustment operation needs the printing period of three latch cycles for each line printing operation. The LED printer with this adjustment control can be increased in its printing speed by reducing the pulse width, but this adjustment is limited. In particular, an LED printer which has a large number of positions for a line of printing cannot easily achieve a desired high speed printing operation. In addition, it is necessary to produce a series of three blocks of corrected data in accordance with the enable signals for each line printing operation, which necessitates a complicated program or control of microprocessor 5.
Accordingly, a current supplying integrated circuit which is capable of adjusting variation in output strength among a plurality of elements to be driven by varying the current intensity supplied to each of the elements is desired.